Low‐power, high‐speed dual modulus prescalers based on branch‐merged true single‐phase clocked scheme
Author:
Affiliation:
1. Key Laboratory of Microelectronic Devices and CircuitsInstitute of Microelectronics, Peking UniversityBeijing100871People's Republic of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2014.4146
Reference9 articles.
1. Pulse swallow frequency divider with idle DFFs automatically powered off;Gao H.;Electron. Lett.,2012
2. A 13.5 mW 5 GHz frequency synthesizer with dynamic‐logic frequency divider;Pellerano S.;IEEE J. Solid‐State Circuits,2004
3. The speed‐power trade‐off in the design of CMOS true‐single‐phase‐clock dividers;Deng Z.;IEEE J. Solid‐State Circuits,2010
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3. Performance Comparison of High-Speed Dual Modulus Prescalers Using Metaheuristic Sizing/Optimization;2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI);2020-08
4. High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler;Electronics;2020-04-28
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