A modified pulse swallow frequency divider for fractional-N PLL-Reference-Cited by-同舟云学术

A modified pulse swallow frequency divider for fractional-N PLL

Published:2020-09-25 Issue:18 Volume:17 Page:20200204-20200204
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yan Peihui¹,Jiang Jinguang¹,Liu Jianghua²,Tang Yanan¹

Affiliation:

1. GNSS Research Center, Wuhan University

2. School of Electronics and Information Engineering, Hubei University of Science and Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/17/18/17_17.20200204/_pdf

Reference30 articles.

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2. [2] J. Shin and H. Shin: “A CMOS high speed pulse swallow frequency divider for ΔΣ fractional-N PLL’s,” IEICE Electron. Express 7 (2010) 856 (DOI: 10.1587/elex.7.856).

3. [3] S. Radhapuram, et al.: “A low-power CMOS programmable frequency divider with novel retiming scheme,” IEICE Electron. Express 12 (2015) 20141233 (DOI: 10.1587/elex.12.20141233).

4. [4] W. Jiang, et al.: “A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler,” IEICE Electron. Express 14 (2017) 20160446 (DOI: 10.1587/elex.13.20160446).

5. [5] J. Wu, et al.: “A low-power high-speed true single phase clock divide-by-2/3 prescaler,” IEICE Electron. Express 10 (2013) 20120913 (DOI: 10.1587/elex.10.20120913).