Latency Analysis in the 2-Dimensional Systolic Arrays for Matrix Multiplication-Reference-Cited by-同舟云学术

Latency Analysis in the 2-Dimensional Systolic Arrays for Matrix Multiplication

Published:2021-03-22 Issue: Volume:15 Page:1-7
ISSN:1998-4308
Container-title:International Journal of Computers
language:en
Short-container-title:

Author:

Snopce Halil¹,Aliu Azir¹

Affiliation:

1. CST Faculty SEE-University Tetovo, Macedonia

Abstract

This paper deals with the latency analysis in a twodimensional systolic array for matrix multiplication. The latency for all possible connection schemes is discussed. In this way there is obtained the lower bound of the latency that can be achieved using such arrays.

Publisher

North Atlantic University Union (NAUN)

Subject

Industrial and Manufacturing Engineering,Environmental Engineering

Reference10 articles.

1. S.Y. Kung, “VLSI Array Processor for Signal Processing,” In Proc. Conf. Advanced Res. Integrated Circuits, 1980.

2. G.J. Li and B.W. Wah, “The design of Optimal Systolic Arrays,” IEEE Trans. On Computers, vol.C-34, pp. 66-77, 1985.

3. A.K. Oudjida, S.Titri, M. Hamerlain, “Mapping Full Systolic Arrays for Matrix Product on XILINX’s XC4000(E,EX) FPGAs”, COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol.21 Iss:1, pp.69-81, 2002.

4. J.C. Tsay and P.Y. Chang, “Design of Efficient Regular Arrays for Matrix Multiplication by Two step Regularization,” IEEE tran. On Parallel and Distributed computing, 1995.

5. H.V. Jagadish and Kailath, “ A family of a new efficient arrays for matrix multiplication”, IEEE Trans. On Computers, vol. 38, pp 149-155, January 1989.

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