Affiliation:
1. CST Faculty SEE-University Tetovo, Macedonia
Abstract
This paper deals with the latency analysis in a twodimensional systolic array for matrix multiplication. The latency for all possible connection schemes is discussed. In this way there is obtained the lower bound of the latency that can be achieved using such arrays.
Publisher
North Atlantic University Union (NAUN)
Subject
Industrial and Manufacturing Engineering,Environmental Engineering
Cited by
2 articles.
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1. EBASA: Error Balanced Approximate Systolic Array Architecture Design;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05
2. Design and Evaluation of Inexact Computation based Systolic Array for Convolution;2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS);2023-02-27