Dual Threshold Voltage Pseudo Domino Logic - Based Buffer with Reduced Power

Abstract

In this paper, a new technique of power reduction in pseudo domino logic-based buffer is proposed with dual threshold voltage. The proposed method employs the dual threshold voltage technique to reduce the power. During the precharge stage, we have used the high threshold voltage transistor in the non-critical path of the circuit, to reduce the leakage current due to which the average power dissipation is minimized. In critical path, low threshold voltage transistors are used. The low threshold voltage transistors are used in evaluation stage, for the performance enhancement of the circuit. Keeper circuit is used with two PMOS transistor which helps in maintaining voltage of dynamic node and improves the noise immunity and speed of the circuit. Also, a NMOS transistor, which is operated by the dynamic node is used which minimizes the leakage by creating a stacking impact. In addition, the clock inverter is enabled via low voltage NMOS which significantly reduces the current in the inverter due to direct connection between the supply voltage (Vdd) to ground.