Author:
Shah Ambika Prasad,Neema Vaibhav,Daulatabad Shreeniwas
Cited by
3 articles.
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1. Dual Threshold Voltage Pseudo Domino Logic - Based Buffer with Reduced Power;IOP Conference Series: Materials Science and Engineering;2022-10-01
2. A Literature Review: Different Leakage Reduction Techniques for CMOS circuits;2021 International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA);2021-10-08
3. DOIND: a technique for leakage reduction in nanoscale domino logic circuits;Journal of Semiconductors;2016-05