Design and Performance Analysis of Partially Depleted and Fully Depleted Silicon on Insulator MOSFET

Abstract

Abstract In this paper, Partially Depleted Silicon on Insulator (PDSOI) MOSFET and Fully Depleted Silicon on Insulator (FDSOI) MOSFET are designed, and the impact of n-type doping concentration, work function variation, gate oxide, and silicon layer thickness on the performance of the device is studied and analyzed. The floating body and associated kink effects present in a PDSOI device are also investigated in detail. In addition to this, comparisons are made between PDSOI and FDSOI MOSFET to analyze their performance for various device parameters. The threshold voltage rises with increasing Si surface thickness and source doping, according to the data found. The drain current increases as the N-type doping concentration develops in both PD and FDSOI MOSFETs, and conduction begins after a concentration of 3x1017 cm−3 for PD and 2x1017 cm−3 for FDSOI, before which conduction is not effective. For the same n-type doping concentration and gate work function, FDSOI has a higher drain current than PDSOI. FDSOI is better than PDSOI since it eliminates PDSOI’s defects and enhances its performance. The Silvaco Atlas-2D TCAD simulator is used to simulate the device using conventional architecture and models.