Comprehensive analysis of fully depleted and partially depleted silicon-on-insulator FET device
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s00542-024-05709-9.pdf
Reference33 articles.
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3. Garg A, Singh B, Singh Y (2021) Dual-gate junctionless FET on SOI for high frequency analog applications. SILICON 13:2835–2843
4. Goel N, Pandey MK (2017) Design device for subthreshold slope in DG fully depleted SOI MOSFET. J Nano-and Electron Phys 9:1022–1031
5. Ikeno K, Matsumoto S (2016) Comparisons of hot-carrier effects of scaled N-Channel and p-channel thin-film SOI power MOSFETs under constant drain electric field. In: Extended Abstract of the 2016 International Conference on Solid State Devices and Materials, pp PS-14-04
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