Substrate Noise Evaluation and Reduction of N-MOSFET Using Optimized Silicone-On-Insulator based on Seagull optimization algorithm-Reference-Cited by-同舟云学术

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Substrate Noise Evaluation and Reduction of N-MOSFET Using Optimized Silicone-On-Insulator based on Seagull optimization algorithm

Published:2023-05-04 Issue: Volume: Page:
ISSN:
Container-title:2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC)
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Author:

Sharma Sanjay¹,Yadav R. P.²,Janyani Vijay²

Affiliation:

1. Malaviya National Institute of Technology Jaipur (MNIT),Department of Electronics and Communication Engineering,Jaipur,Rajasthan,India

2. Malaviya National Institute of Technology Jaipur (MNIT),Department of Electronics and Communication Engineering,Jaipur,Rajasthan,India,302017

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10149803/10149848/10149882.pdf?arnumber=10149882

Reference16 articles.

1. Ultra-Low-Power FDSOI Neural Circuits for Extreme-Edge Neuromorphic Intelligence

2. Study on Impact of Parasitic Capacitance on Performance of Graded Channel Negative Capacitance SOI FET at High Temperature

3. On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

4. A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

5. Suppressing Methods of Parasitic Capacitance Caused Interference in a SiC MOSFET Integrated Power Module

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