DC and analog/RF performance optimisation of source pocket dual work function TFET
Author:
Affiliation:
1. Nanoelectronics and VLSI Lab, PDPM Indian Institute of Information Technology, Design and Manufacturing Jabalpur, Jabalpur, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2017.1335788
Reference16 articles.
1. Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+Layer
2. Scaling the Vertical Tunnel FET With Tunnel Bandgap Modulation and Gate Workfunction Engineering
3. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric
4. Impact of a Spacer Dielectric and a Gate Overlap/Underlap on the Device Performance of a Tunnel Field-Effect Transistor
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