Design of low power 16-bit counter with Programmable Combinational Logic and Integrated Clock Gating using 16-nm technology
Author:
Affiliation:
1. ECE, Vel Tech High Tech Dr.Rangarajan Dr.Sakunthala Engineering College, Chennai, India
2. CSE, RMK Engineering College, Chennai, TN, India
3. ECE, Vel Tech
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2020.1793398
Reference21 articles.
1. Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
2. Performance analysis and implementation of clock gating techniques for low power applications
3. Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures
4. GHz programmable counter with low power consumption
5. Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
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