Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials
Author:
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
http://www.tandfonline.com/doi/pdf/10.1080/00207217.2012.720955
Reference17 articles.
1. Bhuwalka, K.K., Mohapatra, N.R., Narendra, S.G., and Ramgopal Rao, V. (2002), ‘Effective Dielectric Thickness Scaling for High-k Gate Dielectric MOSFETs’, inMaterials Research Society Symposium Proceedings, Vol. 716, pp. B4.19.1–19.5
2. Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric
3. Impact of Halo Doping on the Subthreshold Performance of Deep-Submicrometer CMOS Devices and Circuits for Ultralow Power Analog/Mixed-Signal Applications
4. Integrated Systems Engineering (ISE) TCAD Manuals. Release 10.0; 2006
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