Design and Analysis of Different Full Adder Cells Using New Technologies-Reference-Cited by-同舟云学术

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Design and Analysis of Different Full Adder Cells Using New Technologies

Published:2020-07-26 Issue: Volume: Page:585-597
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Dinesh Kumar Nandhaiahgari,Rajendra Prasad Somineni,Raja Kumari Chilukuri,Dhanunjaya Naidu Challa

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-15-4692-1_45

Reference9 articles.

1. Maleknejad M, Mohammadi S, Mirhosseini SM, Navi K, Naji HR, Hosseinzadeh M (2018) A low-power high-speed hybrid multi-threshold full adder design in CNFET technology. Springer Science+Business Media, LLC, part of Springer Nature

2. Ghanatghestani MM, Ghavami B, Salehpour H (2017) A CNFET full adder cell design for high-speed arithmetic units. Turkish J Electr Eng Comput Sci 25:2399–2509

3. Deng J, Wong HSP (2006) A circuit-compatible SPICE model for enhancement mode carbon nanotube field effect transistors. Int Conf Simul Semicond Process Devices, 166–169

4. Somineni RP, Sai YP, Leela SN (2015) Low leakage CNTFET full adders. In: IEEE 2015 global conference on communication technologies (GCCT), pp 174–179, 23–24 Apr 2015

5. Somineni RP, Jaweed SM (2017) Design of low power multiplier using CNTFET. In: 2017 IEEE 7th international advance computing conference (IACC-2017), Hyderabad, pp 556–559, 05–07 Jan 2017

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Nano Thermal Simulation of Graphene Field Effect Transistor Based on Ballistic Diffusive Model;International Journal of High Speed Electronics and Systems;2024-07-31

2. Low Power Optimization of Full Adder using GNRFET Technology– A Review;2022 8th International Conference on Signal Processing and Communication (ICSC);2022-12-01

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