Low Power Optimization of Full Adder using GNRFET Technology– A Review
Author:
Affiliation:
1. Greater Noida Institute of Technology,Department of Electronics and Communication Engineering,Greater Noida,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009017/10009021/10009085.pdf?arnumber=10009085
Reference12 articles.
1. Design, analysis and performance comparison of GNRFET based 8-bit ALUs
2. CNTFET-Based Design of a High-Efficient Full Adder Using XOR Logic
3. Design and Analysis of Different Full Adder Cells Using New Technologies
4. Design of low threshold Full Adder cell using CNTFET;chandrashekar;International Journal of Applied Engineering Research,2017
5. Modified Low-Power Hybrid 1-Bit Full Adder
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