Modified Low-Power Hybrid 1-Bit Full Adder-Reference-Cited by-同舟云学术

Modified Low-Power Hybrid 1-Bit Full Adder

Published:2017-09-07 Issue: Volume: Page:191-200
ISSN:1876-1100
Container-title:Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications
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Author:

Mannepalli Chaithanya,Kommu Chaitanya

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-4280-5_20

Reference9 articles.

1. C.-K. Tung, Y.-C. Hung, S.-H. Shieh, G.-S. Huang.: A low-power high-speed hybrid CMOS full adder for embedded system, in Proc. IEEE Conf. Design Diagnostics Electron. Circuits Syst., vol. 13, pp. 1–4 (Apr. 2007).

2. S. Goel, A. Kumar, and M. A. Bayoumi.: Design of robust, energy efficient full adders for deep-submicrometer design using hybrid-CMOS logic style, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309–1321, (Dec. 2006).

3. J. M. Rabaey, A. Chandrakasan, and B. Nikolic.: Digital Integrated Circuits: A Design Perspective, 2nd ed. Delhi, India: Pearson Education, (2003).

4. N. H. E. Weste, D. Harris, and A. Banerjee.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed. Delhi, India: Pearson Education, (2006).

5. M. Hosseinghadiry, H. Mohammadi, M. Nadisenejani.: Two New Low Power High Performance Full Adders with Minimum Gates, International Journal of Electronics, Circuits and Systems, Vol. 3, No. 2, pp. 124–131 (2009).

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