A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4295238/4295239/04295280.pdf?arnumber=4295280
Cited by 34 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Comparative analysis of hybrid logic style full adders in multistage structures;AIP Conference Proceedings;2024
2. Design and investigation of 18T & 20T full adder using hybrid logic;AIP Conference Proceedings;2024
3. Area Efficient and Ultra Low Power Full Adder Design Based on GDI Technique for Computing Systems;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024
4. Performance Efficient and Fault Tolerant Approximate Adder;Journal of Electronic Testing;2023-12
5. Optimizing the 12T Hybrid 1-Bit Full Adder Circuit for Low Energy Applications;2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
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