Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders
-
Published:2023-07-06
Issue:
Volume:
Page:
-
ISSN:0218-1266
-
Container-title:Journal of Circuits, Systems and Computers
-
language:en
-
Short-container-title:J CIRCUIT SYST COMP
Author:
Bhau Parthiv1,
Savani Vijay1
Affiliation:
1. Department of Electronics and Communication Engineering, Institute of Technology, Nirma University, S. G. Highway, Ahmedabad 382481, India
Abstract
This paper proposes two 19 transistor (19T) hybrid adder designs based on Fin Field Effect Transistor-Transmission Gate Diffusion Input (FinFET-TGDI) technique. The performance of these designs is compared with various state-of-the-art adders, and the simulations are carried out using 18[Formula: see text]nm FinFET technology in the Cadence Virtuoso tool at a supply voltage of 0.8[Formula: see text]V and nominal temperature. Results show that the proposed adders outperform the conventional Mirror adder, achieving a 25% improvement in maximum propagation delay, a 20% improvement in average power, and a 39% improvement in Power Delay Product (PDP). Both proposed adders also demonstrate significant benefits in terms of Figure of Merit (FoM) when compared with other reported architectures. The simulations also consider variations in the nominal supply voltage of 10% and temperature variations from −55[Formula: see text]C to 125[Formula: see text]C for the PDP of all adders. Furthermore, the post-layout simulation results for both proposed adder architectures under nominal supply voltage are presented. To assess the robustness of the circuits, process corner analysis and Monte Carlo analysis are performed for all adder architectures.
Publisher
World Scientific Pub Co Pte Ltd
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献