Author:
Somineni Rajendra Prasad,Jaweed Shaik Mohammed
Cited by
5 articles.
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1. Design of Strong-Arm Latch Comparator for Low Power 12-bit SAR ADC;2024 International Conference on Integrated Circuits and Communication Systems (ICICACS);2024-02-23
2. Design of DADDA Multiplier Using High Performance and Low Power Full Adder;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
3. Design of Wallace tree multiplier circuit using high performance and low power full adder;E3S Web of Conferences;2023
4. RTL to GDSII Flow Implementation of 8-bit Baugh-Wooley Multiplier;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28
5. Design and Analysis of Different Full Adder Cells Using New Technologies;Lecture Notes in Electrical Engineering;2020-07-26