Low Area-High Speed Architecture of Efficient FIR Filter Using Look Ahead Clock Gating Technique
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-8086-2_33
Reference10 articles.
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3. Daboul S, Hahnle N, Held S, Schorr U (2018) Provably fast and near optimum gate sizing. IEEE Trans on Comput Aided Des Integr Circuits Syst 37(12):3163–3176
4. Tamil Chindhu S, Shanmugasundaram N (2018) Clcok gating techniques: an overview. In: Proceedings in IEEE conference on emerging devices and smart systems
5. Chandrakar K, Roy S (2017) A SAT-based methodology for effective clock gating for power minimization. Accepted Manuscript in JCSC
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