Author:
Chindhu S. Tamil,Shanmugasundaram N.
Cited by
17 articles.
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1. Low-power, high-speed comparator design at 45-nm CMOS for efficient deep learning acceleration;International Journal of Information Technology;2024-07-19
2. Synthesis of a Programmable Clock Management Unit Using Clock Dividers and Clock Gating using 45nm technology;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28
3. Design and Implementation of Low Power Golay Encoder Architecture;2024 5th International Conference for Emerging Technology (INCET);2024-05-24
4. Impact of Clock-Gating on ALU Optimized RISC-V Microarchitectures for Low Power Applications;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
5. Design of Low Power SPI Protocol using Clock Gating Techniques;2024 International Conference on Emerging Technologies in Computer Science for Interdisciplinary Applications (ICETCS);2024-04-22