Synthesis of a Programmable Clock Management Unit Using Clock Dividers and Clock Gating using 45nm technology
Author:
Affiliation:
1. Vidyavardhaka College of Engineering,Department of Electronics and Communication Engineering,Mysuru,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10624684/10624740/10624752.pdf?arnumber=10624752
Reference20 articles.
1. A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS
2. Clock Tree Generation by Abutment in Synchoros VLSI Design
3. A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine
4. Clock Gating Techniques: An Overview
5. Hybrid Adaptive Clock Management for FPGA Processor Acceleration
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