On Generation of Delay Test with Capture Power Safety
Author:
Gulve Rohini,Hage Nihar
Publisher
Springer Singapore
Reference11 articles.
1. Devanathan, V.R., Ravikumar, C.P., Kamakoti, V., Glitch-aware pattern generation and optimization framework for power-safe scan test. In: IEEE 25th VLSI Test Symposium, pp. 167–172. IEEE (2007) 2. Eggersglub, S., Schmitz, K., Krenz-Baath, R., Drechsler, R.: Optimization-based multiple target test generation for highly compacted test sets. In: IEEE 19th European Test Symposium (ETS), pp. 1–6. IEEE (2014) 3. Eggersglüß, S., Drechsler, R.: As-robust-as-possible test generation in the presence of small delay defects using Pseudo-Boolean Optimization. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6. IEEE (2011) 4. Eggersgluss, S., Drechsler, R.: Efficient data structures and methodologies for SAT-based ATPG providing high fault coverage in industrial application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9), 1411–1415 (2011). IEEE 5. Eggersglüß, S., Miyase, K., Wen, X.: SAT-based post-processing for regional capture power reduction in at-speed scan test generation. In: IEEE 21th European Test Symposium (ETS), pp. 1–6. IEEE (2016)
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