Analysis of the Effect of Bias Current on the Performance of MOS Current-Mode Logic Circuits

Author:

Sharma Antriksh,Dwivedi Dileep

Publisher

Springer Singapore

Reference9 articles.

1. Hassan H, Anis M, Elmasry M (2005) Design and optimization of MOS current mode logic for parameter variations. Integr VLSI J 38(3):417–437

2. Gupta K, Pandey N, Gupta M (2013) Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells. Microelectron J 44(6):561–567

3. Sharroush SM (2016) Performance optimization of MOS current-mode logic. In: International conference on electrical, electronics, and optimization techniques (ICEEOT), IEEE, Mar 2016, pp 2915–2920

4. Kang SM, Leblebici Y (2003) CMOS digital integrated circuits. Tata McGraw-Hill Education

5. Musicer JM, Rabaey J (2000) MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments. In: Proceedings of the 2000 international symposium on low power electronics and design, ACM, Aug 2000, pp 102–107

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