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Design and optimization of MOS current mode logic for parameter variations

  • Published:2005-01 Issue:3 Volume:38 Page:417-437
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Hassan Hassan,Anis Mohab,Elmasry Mohamed

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference31 articles.

1. An MOS current mode logic (MCML) circuit for low-power sub-GHz processors;Yamashina;IEICE Trans. Electron.,1992

2. MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments;Musicer,2000

3. Design strategies for source coupled logic gates;Alioto;IEEE Trans. Circuits Systems I,2003

4. Impact of on-chip process variations on MCML performance;Bruma,2003

5. MOSFET Modeling & BSIM3 User's Guide;Cheng,1999

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Introduction;Model and Design of Improved Current Mode Logic Gates;2019-11-23

2. Performance Comparison of MCML and CMOS Inverters at High Operation Frequencies;Lecture Notes in Electrical Engineering;2019

3. Analysis of the Effect of Bias Current on the Performance of MOS Current-Mode Logic Circuits;Lecture Notes in Electrical Engineering;2019

4. Design and Optimization of Differential Ring Oscillator for IR-UWB Applications in 0.18 μm CMOS Technology;Journal of Circuits, Systems and Computers;2017-02-08

5. Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-04
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