Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells-Reference-Cited by-同舟云学术

Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells

Published:2013-06 Issue:6 Volume:44 Page:561-567
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Gupta Kirti,Pandey Neeta,Gupta Maneesha

Publisher

Elsevier BV

Subject

General Engineering

Reference30 articles.

1. Quadrature bandpass ΣΔ modulator for digital radio;Jantzi;IEEE J. Solid-State Circuits,1997

2. Radio frequency digital-to-analog converter;Luschas;IEEE J. Solid-State Circuits,2004

3. A bit-stream digital-to-analog converter with 18-b resolution;Kup;IEEE J. Solid-State Circuits,1991

4. T. Takaramoto, S. Harajiri, M. Sawada, O. Kobayashi, K. Gotoh, A. bonded-SOI-wafer, CMOS 16-bit 50-KSPS delta-sigma ADC, in: Proceedings of IEEE Custom Integrated Circuit Conference, 1991, pp. 18.1.1–18.1.4.

5. Principles of CMOS VLSI Design: A system perspective Reading;Weste,1993

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