Advancements in Back End of Line Technology: Enhancing Semiconductor Manufacturing Efficiency
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-6649-3_49
Reference12 articles.
1. Andric S, Ohlsson L, Wenrersson L-E. Low-temperature front-side BEOL technology with circuit level multiline Thru-reflect-line kit for III-V MOSFETs on Silicon. In: 2019 92nd ARFTG microwave measurement conference (ARFTG). Orlando; 2019. p. 1–4. https://doi.org/10.1109/ARFTG.2019.8637222.
2. Colgan EG, Polastre RJ, Knickerbocker J, Wakil J, Gambino J, Tallman K. Measurement of back end of line thermal resistance for 3D chip stacks. In: 29th IEEE semiconductor thermal measurement and management symposium. San Jose; 2013. p. 23–8. https://doi.org/10.1109/SEMI-THERM.2013.6526800.
3. Cui B, et al. Back-end-of-line compatible HfO2/ZrO2 superlattice ferroelectric capacitor with high endurance and remnant polarization. IEEE Electron Device Lett. 2023;44(6):1011–4. https://doi.org/10.1109/LED.2023.3265516.
4. Kuo P-Y, Lo S-C, Wei H-H, Liu P-T. Asymmetric low metal contamination NI-induced lateral crystallization polycrystalline-silicon thin-film transistors with low OFF-state currents for Back-End of Line (BEOL) compatible devices applications. IEEE J Electron Devices Soc. 2020;8:1317–22. https://doi.org/10.1109/JEDS.2020.3030962.
5. Carta F, Gates SM, Limanov AB, Im JS, Edelstein DC, Kymissis I. Sequential lateral solidification of silicon thin films on Cu BEOL-integrated wafers for monolithic 3-D integration. IEEE Trans Electron Devices. 2015;62(11):3887–91. https://doi.org/10.1109/TED.2015.2479087.
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