Measurement of back end of line thermal resistance for 3D chip stacks-Reference-Cited by-同舟云学术

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Measurement of back end of line thermal resistance for 3D chip stacks

Published:2013-03 Issue: Volume: Page:
ISSN:
Container-title:29th IEEE Semiconductor Thermal Measurement and Management Symposium
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Author:

Colgan E. G.,Polastre R. J.,Knickerbocker J.,Wakil J.,Gambino J.,Tallman K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6520965/6526787/06526800.pdf?arnumber=6526800

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Experimentally Validated Thermal Modeling Prediction for BEOL and BSPDN Stacks;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. Advancements in Back End of Line Technology: Enhancing Semiconductor Manufacturing Efficiency;Handbook of Emerging Materials for Semiconductor Industry;2024

3. Thermal Evaluation for Monolithic 3D Integrated Circuits Based on Gate-all-Around Transistors;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

4. Thermal analysis of advanced back-end-of-line structures and the impact of design parameters;2022 21st IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (iTherm);2022-05-31

5. Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging;Journal of Electronic Packaging;2020-06-29

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