Author:
Sai Mounika Avvaru,Sripriya Chilakapati,Sarada V.
Reference14 articles.
1. Xiang D, Wen X, Wang LT (2016) Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(3):942–953
2. Kanimozhi P, Ramalingam S, Murugesan S, Ramya N (2017) Input vector observing simultaneous BIST architecture utilizing SRAM cells. Int J Sci Res Sci Technol (IJSRST) 3(8):506–514
3. Wang S, Gupta SK (2006) LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans Comput Aided Des Integr Circuits Syst 25(8):1565–1574
4. Bagalkoti A, Shirol SB, Ramakrishna S, Kumar P, Rajashekar BS (2019) Design and implementation of 8-bit LFSR, bit-swapping LFSR and weighted random test pattern generator: a performance improvement. In: 2019 International conference on intelligent sustainable systems (ICISS). IEEE, pp 82–86
5. Tyszer J, Filipek M, Mrugalski G, Mukherjee N, Rajski J (2013) New test compression scheme based on low power BIST. In: 2013 18th IEEE european test symposium (ETS). IEEE, pp 1–6
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