Reduced complexity XOR trees for LDPC codes and BS-LFSR techniques to High-Speed memory applications

Author:

Sadhika P.,Thuraka Esther Rani,Rao Rameshwar

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference43 articles.

1. High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems;Suravi,2022

2. A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders;Song;IEEE Transactions on Very Large-Scale Integration (VLSI) Systems,2022

3. Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver;Huo;Wirel Commun Mob Comput,2022

4. Pourjabar s and Choi G.S: A high‐throughput multimode low‐density parity‐check decoder for 5G New Radio.International Journal of Circuit Theory and Applications, 2022, pp. 1365-1374.

5. Gupta K. and Raman A: Design of Low-Power Bit Swapping BIST for IC Self-testing. InInnovations in Electronics and Communication Engineering Springer, Singapore, 2022, pp.569-577.

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