A “Digital+CIM” Processor Supporting Large-Scale NN Models
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-3477-1_6
Reference11 articles.
1. Yue J, Liu Y, Feng X, He Y, Wang J, Yuan Z, Zhan M, Liu J, Su J-W, Chung Y-L et al (2023) An energy-efficient computing-in-memory NN processor with set-associate blockwise sparsity and ping-pong weight update. IEEE J Sol-State Circ
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3. Yang J, Kong Y, Wang Z, Liu Y, Wang B, Yin S, Shi L (2019) 24.4 sandwich-RAM: an energy-efficient in-memory BWN architecture with pulse-width modulation. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 394–396
4. Su J-W, Si X, Chou Y-C, Chang T-W, Huang W-H, Tu Y-N, Liu R, Lu P-J, Liu T-W, Wang J-H et al (2020) 15.2 A 28 nm 64 kB inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 240–242
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