Reversible Fade Gate as Decoder, Encoder and Full Adder-Reference-Cited by-同舟云学术

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Reversible Fade Gate as Decoder, Encoder and Full Adder

Published:2021 Issue: Volume: Page:1323-1331
ISSN:1876-1100
Container-title:Advances in Automation, Signal Processing, Instrumentation, and Control
language:
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Author:

Krishnaveni D.,Kiran N.,Shalini H. N.,Geetha Priya M.

Publisher

Springer Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-15-8221-9_123

Reference26 articles.

1. Geetha Priya M, Baskaran K, Krishnaveni D (2012) Leakage power reduction techniques in deep submicron technologies for VLSI applications. Procedia Eng 30:1163–1170

2. Geetha Priya M, Baskaran K, Krishnaveni D, Srinivasan S (2012) A new leakage power reduction techniques for CMOS VLSI circuits. J Artif Intell 5:227–232

3. Landauer R (1961) Irreversibility and heat generation in the computing process. IBM J Res Dev 3:183–191

4. Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 525–532

5. Thapliyal H, Ranganathan N (2010) Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J Emerg Technol Comput Syst 6(4):31. (Article 14)

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1. State of the art design of adder modules: performance validation of GDI methodology for energy harvesting applications;International Journal of System Assurance Engineering and Management;2023-07-26

2. State of Art Design: Novel Realization of FinFET based Adder Cells;2022 International Conference on Augmented Intelligence and Sustainable Systems (ICAISS);2022-11-24

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