Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process-Reference-Cited by-同舟云学术

Novel multiple-selected and multiple-valued memory design using negative differential resistance circuits suitable for standard SiGe-based BiCMOS process

Published:2008-09-16 Issue:2 Volume:59 Page:161-167
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Gan Kwang-Jow,Tsai Cher-Shiung,Liang Dong-Shong

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-008-9216-3.pdf

Reference17 articles.

1. Chen, K. J., Maezawa, K., & Yamamoto, M. (1996). InP-based high-performance monostable-bistable transition logic elements (MOBILE’s) using integrated multiple-input resonant-tunneling devices. IEEE Electron Device Letters, 17(3), 127–129.

2. Avedillo, M. J., Quintana, J. M., & Pettenghi, H. (2006). Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Transactions on Circuits and Systems II: Express Briefs, 53(5), 334–338.

3. Choi, S., Lee, B., Kim, T., & Yang, K. (2004). CML-type monostable bistable logic element (MOBILE) using InP-based monolithic RTD/HBT technology. Electronics Letters, 40(13), 792–793.

4. Seabaugh, A. C., Kao, Y. C., & Yuan, H. T. (1992). Nine-state resonant tunneling diode memory. IEEE Electron Device Letters, 13(9), 479–481.

5. Yan, Z. X., & Deen, M. J. (1992). A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load. IEEE Journal of Solid-State Circuits, 27(8), 1198–1202.

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Band‐to‐Band Tunneling Control by External Forces: A Key Principle and Applications;Advanced Electronic Materials;2022-12-04

2. Negative Differential Resistance in Boron Nitride Graphene Heterostructures: Physical Mechanisms and Size Scaling Analysis;Scientific Reports;2015-05-20

3. A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits;Analog Integrated Circuits and Signal Processing;2015-01-21

4. Negative Differential Resistances Observed In Suspended-Channel FETs;AIP Conference Proceedings;2011