Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz–3.8 GHz-Reference-Cited by-同舟云学术

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Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz–3.8 GHz

Published:2021-01-02 Issue:1 Volume:107 Page:101-108
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Pradhan Nigidita^ORCID,Jana Sanjay Kumar

Funder

Ministry of Electronics and Information Technology, Govt. of India

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-020-01779-7.pdf

Reference18 articles.

1. Chen, O. T. C., & Sheen, R. R.-B. (2002). A power-efficient wide-range phase-locked loop. IEEE Journal of Solid-State Circuits, 37(1), 51–62.

2. Razavi, B. (2002). Design of analog CMOS integrated circuits. Chennai: Tata McGraw-Hill Education.

3. Chiu, W. H., Huang, Y. H., & Lin, T. H. (2010). A dynamic phase error compensation technique for fast-locking phase-locked loops. IEEE Journal of Solid-State Circuits, 11(6), 1137–1149.

4. Tang, Y., & Geiger, R. L. (2002). Phase detector for PLL-based high-speed data recovery. Electronics Letters, 38(23), 1417–1419.

5. Kumar, N., & Kumar, M. (2016). Design of low power and high speed phase detector. In 2016 2nd International Conference on Contemporary Computing and Informatics (IC3I), pp 676–680.

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