Performance analysis for reliable nanoscaled FinFET logic circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-020-01765-z.pdf
Reference16 articles.
1. Zimpeck, A. L., Meinhardt, C., & Reis, R. A. (2015). Impact of PVT variability on 20 nm FinFET standard cells. Microelectronics Reliability, 55(9–10), 1379–1383.
2. Roy, K., Mukhopadhyay, S., & Mahmoodi-Meimand, H. (2003). Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proceedings of the IEEE, 91(2), 305–327.
3. Manju, I., & Kumar, A. S. (2015). A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time. Analog Integrated Circuits and Signal Processing, 84(1), 119–126.
4. Dadoria, A. K., Khare, K., Gupta, T. K., & Singh, R. P. (2017). Ultra-low power FinFET-based domino circuits. International Journal of Electronics, 104(6), 952–967.
5. Magraiya, V. K., & Gupta, T. K. (2019). ONOFIC pull-up approach in domino logic circuits using FinFET for subthreshold leakage reduction. Circuits, Systems, and Signal Processing., 38(6), 2564–2587.
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