Abstract
Abstract
Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors.The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn’t entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach.The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18% and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parametres in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability.This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.