A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time

Author:

Manju I.,Senthil Kumar A.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference33 articles.

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2. Alioto, M. (2012). Ultra-low power VLSI circuit design demystified and explained: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(1), 3–29.

3. Keerthi, R. & Chen, C. (2008). Stability and static noise margin analysis of low-power SRAM. In Instrumentation and Measurement Technology Conference Proceedings.

4. Mukherjee, D., Mondal, H. K., & Reddy, B. V. R. (2010). Static noise margin analysis of SRAM cell for high speed application. IJCSI International Journal of Computer Science Issues, 7(5), 1–6.

5. Hodges, D.A., Jackson, H. G., & Saleh, R. A. (2003) Analysis and design of digital integrated circuits. Berkeley, McGraw Hill Science Engineering (pp. 3–118).

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