Stability and Static Noise Margin Analysis of Low-Power SRAM-Reference-Cited by-同舟云学术

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Stability and Static Noise Margin Analysis of Low-Power SRAM

Published:2008-05 Issue: Volume: Page:
ISSN:
Container-title:2008 IEEE Instrumentation and Measurement Technology Conference
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Author:

Keerthi Rajasekhar,Chen Chein-in Henry

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4539706/4546978/04547314.pdf?arnumber=4547314

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architectural Designs and Performance Analysis of Adiabatic-based 6T, 9T, and 12T SRAM Cells;2022 International Conference on Automation, Computing and Renewable Systems (ICACRS);2022-12-13

2. An Experimental Evaluation of Resistive Defects and Different Testing Solutions in Low-Power Back-Biased SRAM Cells;Electronics;2022-01-10

3. A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time;Analog Integrated Circuits and Signal Processing;2015-04-28

4. A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM;2010 23rd International Conference on VLSI Design;2010-01

5. Dual Word Line 6-Transistor SRAM Array Architecture;AIP Conference Proceedings;2010

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