A sub-threshold 10T FinFET SRAM cell design for low-power applications
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference37 articles.
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5. A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time;Manju;Analog Integr Circ Sig Process,2015
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1. Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology;International Journal of Circuit Theory and Applications;2024-06-27
2. A FinFET-based low-power, stable 8T SRAM cell with high yield;AEU - International Journal of Electronics and Communications;2024-02
3. Improved Stability for Robust and Low-Power SRAM Cell using FinFET Technology;Journal of Circuits, Systems and Computers;2023-10-28
4. Review of the Nanoscale FinFET Device for the Applications in Nano-regime;Current Nanoscience;2023-09
5. A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications;International Journal of Electronics;2023-07-25
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