A robust multi-bit soft-error immune SRAM cell for low-power applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-023-02144-0.pdf
Reference67 articles.
1. Pal, S., Bose, S., Ki, W.-H., & Islam, A. (2019). Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications. IEEE Transactions on Electron Devices, 67, 80–89.
2. Lorenzo, R., & Pailly, R. (2020). Single bit-line 11T SRAM cell for low power and improved stability. IET Computers & Digital Techniques, 14, 114–121.
3. Kulkarni, J. P., & Roy, K. (2011). Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20, 319–332.
4. Ataei, S., Stine, J. E., & Guthaus, M. R. (2016). A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. In 2016 IEEE 34th international conference on computer design (ICCD) (499–506).
5. Sharma, V., Gopal, M., Singh, P., Vishvakarma, S. K., & Chouhan, S. S. (2019). A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications. Analog Integrated Circuits and Signal Processing, 98, 331–346.
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