Single bit‐line 11T SRAM cell for low power and improved stability-Reference-Cited by-同舟云学术

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Single bit‐line 11T SRAM cell for low power and improved stability

Published:2020-03-31 Issue:3 Volume:14 Page:114-121
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Lorenzo Rohit¹,Pailly Roy¹

Affiliation:

1. Department of EEEIIT GuwahatiAssamIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2019.0234

Reference28 articles.

1. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

2. Flexible circuits and architectures for ultralow power;Calhoun B.H.;Proc. IEEE,2010

3. Ultralow‐voltage, minimum‐energy CMOS;Hanson S.;IBM J. Res. Dev.,2006

4. Okumura S. Iguchi Y. Yoshimoto S. et al.: ‘A 0.56‐V 128 kb 10T SRAM using column line assist (CLA) scheme’.10th Int. Symp. on Quality Electronic Design San Jose CA 2009 pp.659–663

5. Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS

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1. A Descriptive Analysis of Different Dual-Port and Single-Port 11T SRAM Cells for Low-Voltage Operations;Lecture Notes in Electrical Engineering;2024

2. Schmitter trigger-based single-ended stable 7T SRAM cell;Analog Integrated Circuits and Signal Processing;2023-09-23

3. Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology;Engineering Research Express;2023-09-01

4. Design and analysis of radiation hardened 10 T SRAM cell for space and terrestrial applications;Microsystem Technologies;2023-07-12

5. 10T SRAM cell Analysis for improved Read and Write Noise Margin;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06

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