A low power static noise margin enhanced reliable 8 T SRAM cell
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Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s00542-024-05662-7.pdf
Reference30 articles.
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3. Ahmad S, Iqbal B, Alam N, Hasan M (2018) Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis. IEEE Trans Device Mater Reliab 18(3):337–349
4. Aly RE, Bayoumi MA (2007) Low-power cache design using 7T SRAM cell. IEEE Trans Circuits Syst II Express Briefs 54(4):318–322
5. Calhoun BH, Chandrakasan AP (2006) Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J Solid-State Circuits 41(7):1673–1679
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1. Design of dual port 9T SRAM cell with parallel processing and high performance computing;Physica Scripta;2024-08-20
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