FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-022-02052-9.pdf
Reference45 articles.
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4. Bonetti, A., Golman, R., Giterman, R., Teman, A., & Burg, A. (2020). Gain-cell embedded DRAMs: Modeling and design space. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(3), 646–659.
5. Teman, A., Meinerzhagen, P., Burg, A. and Fish, A. (2012). Review and classification of gain cell eDRAM implementations. In 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel IEEE (pp. 1–5).
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