56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-018-1186-5/fulltext.html
Reference15 articles.
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2. Wang, C.-C., Lee, C.-L., & Lin, W.-J. (2007). A 4-Kb low power SRAM design with negative word-line scheme. IEEE Transactions on Circuits & Systems I : Regular Papers, 54(5), 1069–1076.
3. Wang, C.-C., Sung, G.-N., Lee, C.-L., Chen, T.-H., Lin, W.-J., & Hu, R. (2008). 1.7-ns access time SRAM using wordline-controlled transistors with variable bulk bias. Journal of Circuits, Systems, and Computers (JCSC), 17(5), 943–956.
4. Yang, B.-D. (2010). A low-power SRAM using bit-line charge-recycling for read and write operations. IEEE Journal of Solid-State Circuits, 43(2), 2173–2183.
5. Morifuji, E., Yoshida, T., Kanda, M., Matsuda, S., Yamada, S., & Matsuoka, F. (2006). Supply and threshold-voltage trends for scaled logic and SRAM MOSFETs. IEEE Transactions on Electron Devices, 53(6), 1427–1432.
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