A 1.7-ns ACCESS TIME SRAM USING VARIABLE BULK BIAS WORDLINE-CONTROLLED TRANSISTORS

Abstract

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the VTH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V ).