New SRAM design using body bias technique for low-power and high-speed applications-Reference-Cited by-同舟云学术

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New SRAM design using body bias technique for low-power and high-speed applications

Published:2013-04-24 Issue:11 Volume:42 Page:1189-1202
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Faraji Rasoul¹,Naji Hamid Reza¹,Rahimi-Nezhad Majid¹,Arabnejhad Mohammad¹

Affiliation:

1. Department of Electrical and Computer Engineering; Graduate University of Advanced Technology; Kerman IRAN

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cta.1914/fullpdf

Reference24 articles.

1. Adaptive Body Bias for Reducing the Impacts of NBTI and Process Variations on 6T SRAM Cells;Mostafa;IEEE Transactions on Circuits and Systems,2011

2. A 1.7-ns access time SRAM using variable bulk bias wordline-controlled transistors;Wang;Journal of Circuits, Systems, and Computers,2008

3. A Look-ahead Active Body-biasing scheme for SOI-SRAM with dynamic VDDM control;Seto;IEICE Electronics Express,2009

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application;Circuits, Systems, and Signal Processing;2022-01-13

2. A High-Level Model of the Read-Write Control System of a SRAM Chip;2021 IEEE 4th International Conference on Electronics and Communication Engineering (ICECE);2021-12-17

3. Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm;Microprocessors and Microsystems;2021-09

4. A 32 nm single-ended single-port 7T static random access memory for low power utilization;Semiconductor Science and Technology;2021-07-27

5. An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders;International Journal of Circuit Theory and Applications;2021-06-08

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