Design and analysis of a high speed double-tail comparator with isomorphic latch-preamplifier pairs and tail bootstrapping

Author:

Rahmani S.,Ghaznavi-Ghoushchi M. B.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference24 articles.

1. Wicht, B., Nirschl, T., & Schmitt-Landsiedel, D. (2004). Yield and speed optimization of a latch-type voltage sense amplifier. IEEE Journal of Solid-State Circuits, 39, 1148–1158.

2. Sharuddin, I. B., & Lee, L. (2014). An ultra-low power and area efficient 10 bit digital to analog converter architecture. In Presented at the ICSE 2014.

3. Kowsalya, V. (2014). Design of a low power double tail comparator using gated clock and power gating techniques. International Journal of Review in Electronics & Communication Engineering (IJRECE), 2, 29–33.

4. Babayan-Mashhadi, S., & Lotfi, R. (2014). Analysis and design of a low-voltage low-power double-tail comparator. Transaction on Very Large Scale Integration (VLSI) Systems, 22, 343–352.

5. Li, J., Weisheng, X., & Youling, Y. (2010). A high-speed and high-resolution CMOS comparator with three-stage preamplifier. Journal of Semiconductors, 31, 1–5.

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