Author:
Jogad Seema,Akhoon M. Saqib,Loan Sajad A.
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference35 articles.
1. Danesh, S., Hurwitz, J., Findlater, K., Renshaw, D., & Henderson, R. (2013). A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit highly time-interleaved counter ADC with low power comparator design. IEEE Journal of Solid-State Circuits, 48, 733–748.
2. Gupta, R., Gupta, R., & Sharma, S. (2017). Design of high speed and low power 4-bit comparator using FGMOS. AEU—International Journal of Electronics and Communications, 76, 125–131.
3. Khorami, A., & Sharifkhani, M. (2016). High-speed low-power comparator for analog to digital converters. AEU International Journal of Electronics and Communications, 70, 886–894.
4. De La Fuente-Cortes, G., Espinosa Flores-Verdad, G., Gonzalez-Diaz, V. R., & Diaz-Mendez, A. (2017). A new CMOS comparator robust to process and temperature variations for SAR ADC converters. Analog Integrated Circuits Signal Process, 90, 301–308.
5. Goll, B., & Zimmermann, H. (2009). A comparator with reduced delay time in 65-Nm CMOS for supply voltages down to 065 V. IEEE Transactions on Circuits and Systems II: Express Briefs, 56, 810–814.
Cited by
8 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献