Si nanowire FET and its modeling

Author:

Iwai Hiroshi,Natori Kenji,Shiraishi Kenji,Iwata Jun-ichi,Oshiyama Atsushi,Yamada Keisaku,Ohmori Kenji,Kakushima Kuniyuki,Ahmet Parhat

Publisher

Springer Science and Business Media LLC

Subject

General Computer Science

Reference24 articles.

1. Iwai H. Roadmap for 22 nm and beyond. Microelectron Eng, 2009, 86: 1520–1528

2. Suk S D, Lee S Y, Kim S M, et al. High performance 5 nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability. In: IEDM, 2005. 717–720

3. Singh N, Lim F Y, Fang W W, et al. Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. In: IEDM, 2006. 383–386

4. Ernst T, Dupre C, Isheden C, et al. Novel 3D integration process for highly scalable nano-beam stacked-channels GAA (NBG) Fin FETs with HfO2/TiN gate stack. In: IEDM, 2006. 997–1001

5. Tian Y, Huang R, Wang Y, et al. New self-aligned silicon nanowire transistors on bulk substrate fabricated by Epi-free compatible CMOS technology: Process integration, Experimental characterization of carrier transport and low frequency noise. In: IEDM, 2007. 895–899

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