Automatic Abstraction for Verification of Timed Circuits and Systems?-Reference-Cited by-同舟云学术

Automatic Abstraction for Verification of Timed Circuits and Systems?

Published:2001 Issue: Volume: Page:182-193
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
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Author:

Zheng Hao,Mercer Eric,Myers Chris

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-44585-4_16

Reference29 articles.

1. R. Alur and R. P. Kurshan. Timing analysis in cospan. In Hybrid Systems III. Springer-Verlag, 1996.

2. Peter A. Beerel, Teresa H.-Y. Meng, and Jerry Burch. Efficient verification of determinate speed-independent circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 261–267. IEEE Computer Society Press, November 1993.

3. W. Belluomini, C. J. Myers, and H. P. Hofstee. Verification of delayed-reset domino circuits using ATACS. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 3–12, April 1999.

4. W. Belluomini and C.J. Myers. Verification of timed systems using posets. In International Conference on Computer Aided Verification. Springer-Verlag, 1998.

5. Lect Notes Comput Sci;G. Berthelot,1986

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