Author:
Belluomini W.,Myers C.J.,Hofstee H.P.
Cited by
7 articles.
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1. Automating the Design of Asynchronous Logic Control for AMS Electronics;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2020-05
2. Synthesis from Waveform Transition Graphs;2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2019-05
3. Verifying Timed, Asynchronous Circuits using ACL2;2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2019-05
4. Timing constraints for domino logic gates with timing-dependent keepers;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2003-01
5. Automatic Abstraction for Verification of Timed Circuits and Systems?;Computer Aided Verification;2001