Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/article/10.1007/s10836-019-05774-3/fulltext.html
Reference25 articles.
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3. Nunes C, Butzen PF, Reis AI, Ribas RP (2013) BTI, HCI and TDDB aging impact in flip- flops. Elsevier J Microelectron Reliab 53(9–11):1355–1359. https://doi.org/10.1016/j.microrel.2013.07.044
4. Taghipour SH, Niaraki Asli R (2017) Aging comparative analysis of high-performance FinFET and CMOS flip-flops. Elsevier J Microelectron Reliab 69:52–59. https://doi.org/10.1016/j.microrel.2016.12.012
5. Rebaud B, Belleville M, Bernard C, Robert M, Maurine P, Azemard N (2008) A comparative study of variability impact on static flip-flop timing characteristics. IEEE Int Conf Integrated Circuit Design and Technology (ICICDT), June 2–4, 2008, pp. 167–170, https://doi.org/10.1109/ICICDT.2008.4567271
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